1. Field of the Invention
The present invention generally relates to a semiconductor integrated circuit device and a method of producing the same. More particularly, the present invention relates to a configuration of logic cells of a CMOS-type gate array and a method of producing functional blocks by using the logic cells.
2. Related Background Art
In recent years, semiconductor integrated circuit devices (hereinafter, referred to as an “LSI”) have tended toward higher integration and higher performance along with a finer process. This causes the development cost and development period of an LSI to increase. Under such circumstances, an LSI including gate array cells is suitable for the shortening of a development period and the reduction in cost or the flexible production, and finds wide applications, because such a method of producing an LSI can be designed with only wiring patterns by using CAD or the like.
Hereinafter, the configuration of a conventional gate array LSI will be described with reference to the drawings. FIG. 9 is a sectional view showing a layout of conventional gate array cells. Reference numerals 940A and 940B denote CMOS-type base cells, respectively. Reference numeral 980 denotes N-channel transistor regions or P-channel transistor regions in the base cells 940A and 940B, and reference numeral 990 denotes gates. Wiring patterns are formed so as to connect the transistor regions 980 or the gates 990 to first wiring layers 201 through contact VIAs 101, whereby logic cells are formed.
The logic cells 900A and 900B constituted as described above have an arbitrary number of connecting pins 954 for connecting the logic cells to each other and are connected to each other through contact VIAs 112, second wiring layers 202, contact VIAs 123, and a third wiring layer 203. If required, it is possible to form logic cells of multi-layered wiring by connecting the first wiring layers 201 and the second wiring layers 202 through the contact VIAs 112 and the second wiring layers 202 and the third wiring layer 203 through the contact VIAs 123. In most cases, ordinary logic cells can be formed by using up to third wiring layers 203. In this case, it is appreciated that the logic cells are connected by using further upper wiring layers.
In producing the above-described gate array cells, the process of producing up to the base cells 940A and 940B is completed when the logic design of an LSI starts and a mask for wiring layers is produced (master slice system). From then, the remaining wiring process can be carried out, which results in a shortened development period and a reduction in the design cost of an LSI.
However, the configuration of the conventional gate array LSI and a production method thereof have the following problems.
Multi-layered wiring tends to be increased in the number of the wiring layers along with a recent finer process. For example, as shown in FIG. 9, when a functional block 400 is designed with five wiring layers and the logic cells 900A and 900B composed of a gate array have three wiring layers including connections between the logic cells, the logic cell 900B is connected to the functional block 400 through a contact VIA 134, a fourth wiring layer 204, a contact VIA 145, a fifth wiring layer 205, and a connecting pin 955.
Therefore, the period of a wiring process increases, and when logic corrections are needed, the number of correction masks increases, which prevents the shortening of a development period and the reduction in design cost that are characteristics of a gate array LSI.